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SM5K3/SM5K4/SM5K5
SM5K3/SM5K4 SM5K5
DESCRIPTION
The SM5K3/5K4/5K5 are CMOS 4-bit single-chip microcomputers incorporating 4-bit parallel processing function, ROM, RAM, 10-bit A/D converter and timer/counters. It provides three kinds of interrupts and 4 levels subroutine stack. Being fabricated through CMOS process, the chip requires less power and available in a small package : best suitable for Low power controlling, compact equipment like a precision charger.
4-Bit Single-Chip Microcomputers (Controllers With 10-Bit A/D Converter)
FEATURES
* * * * * ROM capacity : 2 048 x 8 bits RAM capacity : 128 x 4 bits Instruction sets : 50 Subroutine nesting : 4 levels I/O port : Input 8 Output 4 Input/output 12 (36QFP/32SOP) 11 (30SDIP) 8 (28SOP) Interrupts : Internal interrupt x 1 (timer) External interrupt x 2 (2 external interrupt inputs) A/D converter : Resolution 10 bits Channels 4 Timer/counter : 8-bit x 1 Built-in main clock oscillator for system clock Ceramic/crystal oscillator (SM5K3/5K5) CR oscillator (SM5K4) Signal generation for real time clock (SM5K3/5K5) Built-in 15 stages divider (for real time clock : SM5K3/5K5)
* Instruction cycle time : 1 s (MIN.) (2 MHz, at 5 V 10%) (SM5K3/5K5) 2 s (MIN.) (1 MHz, at 2.2 to 5.5 V) (SM5K3/5K5) 1 s (MIN.) (1.67 MHz 20%, at 5 V 10%) (SM5K4) * Large current output pins (LED direct drive) : 15mA (TYP.) x 4 (sink current) * Supply voltages : 2.2 to 5.5 V (SM5K3/5K5) 2.7 to 5.5 V (SM5K4) * Packages : 30-pin SDIP (SDIP030-P-0400) 32-pin SOP (SOP032-P-0525) 36-pin QFP (QFP036-P-1010) 28-pin SOP (SOP028-P-0450) (SM5K3/5K5) 24-pin SSOP (SSOP024-P-0275) (SM5K4)
In case of using crystal oscillator
*
*
* *
* *
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
-1-
SM5K3/SM5K4/SM5K5
PIN CONNECTIONS
TOP VIEW 30-PIN SDIP
P53 P41 P42 P43 P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GND P40 AGND P33 P32 P31 P30 VR RESET VDD OSCOUT OSCIN P23 P51 P50
32-PIN SOP
P53 P41 P42 P43 P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 GND P52 P40 AGND P33 P32 P31 P30 VR RESET VDD OSCOUT OSCIN P23 P51 P50
36-PIN QFP
36 35 34 33 32 31 30 29 28 P13 P12 P11 P10 (NC) P03 P02 P01 P00 P20 P21 P22 (NC) GND P50 P51 P23 OSCIN 1 2 3 4 5 6 7 8 9
27 26 25 24 23 22 21 20 19
P43 P42 P41 P53 GND (NC) P52 P40 AGND
10 11 12 13 14 15 16 17 18 OSCOUT VDD RESET VR (NC) P30 P31 P32 P33
28-PIN SOP (SM5K3/5K5)
P41 P42 P43 P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND P40 AGND P33 P32 P31 P30 VR RESET VDD OSCOUT OSCIN P23 GND
24-PIN SSOP (SM5K4)
P41 1 P42 2 P43 3 P00 4 P01 5 P02 6 P03 7 P10 8 P11 9 P20 10 P21 11 P22 12
24 23 22 21 20 19 18 17 16 15 14 13
GND P40 AGND P32 P31 P30 VR RESET VDD OSCOUT OSCIN P23
-2-
SM5K3/SM5K4/SM5K5
BLOCK DIAGRAM
ROM
2 048-BYTE
INST.DEC.
RAM
128 x 4-BIT
DEC
DEC
X (4)
A (4)
C
VDD GND
PU (5)
PL (6)
BM (4)
BL (4)
ALU
SR x 4
SR (8)
SELECTOR
RC
RB RA
RE IME
INTERRUPT CONTROLLER
PRESCALER
R8 R9
OSCIN OSCOUT
OSC IFT IFA IFB
INT A/D
VR AGND
FR
R3
RESET P0 P1 P2 P3 P4 P5
P00
P01
P02
P03
P10
P11
P12
P13
P20
P21
P22
P23
P30
P31
P32
P33
P40
P41
P42
P43
P50
P51
P52
Nomenclature
A A/D ALU BM, BL C IFA, IFB, IFT IME INST. DEC. : : : : : : : : A register A/D converter unit Arithmetic logic unit RAM address register Carry flag Interrupt request flag Interrupt master enable flag Instruction decoder INT : P0-P5 : PU, PL : R8, R9, RC, RE, RF : RA : RB : SB : SR : Interrupt control unit Port register Program counter Mode register Count register Modulo register SB register Stack register
-3-
P53
SM5K3/SM5K4/SM5K5
PIN DESCRIPTION
SYMBOL P00-P03 P10-P11 P12-P13 P20-P23 P30-P33 P40-P43, P50-P53 OSCIN, OSCOUT RESET VR, AGND VDD, GND I/O O I I I/O I I/O I/O I I I FUNCTION High current output (sink current 15 mA) Input (standby release) (counter input : P11) with pull-up resistor Input (standby release) with pull-up resistor Input (with pull-up resistor) or output (independent) Input (also used as analog input) with pull-up resistor Input (with pull-up resistor) and output Ceramic/crystal oscillation pin (SM5K3/5K5)/CR oscillation pin (SM5K4) Reset signal input with pull-up resistor A/D converter reference supply input port Power supply, Ground
NOTE :
Symbols apply to 32-pin SOP and 36-pin QFP. (In case of 30-pin SDIP, P52 does not exist. In case of 28-pin SOP, P50-P53 do not exist. In case of 24-pin SSOP, P12, P13, P33, P50-P53 pins do not exist.)
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply voltage Input voltage Output voltage Maximum output current SYMBOL VDD VI VO IOH IOL0 IOL1 Total output current Operating temperature Storage temperature IOH IOL TOPR TSTG CONDITIONS RATING -0.3 to +7.0 -0.3 to VDD+0.3 -0.3 to VDD+0.3 4 30 4 20 80 -20 to +70 (SM5K3/5K5) -20 to +85 (SM5K4) -55 to +150 UNIT V V V mA mA mA mA mA C C
High-level output current (all outputs) Low-level output current (P00-P03) Low-level output current (all but P00-P03) High-level output current (all outputs) Low-level output current (all outputs)
-4-
SM5K3/SM5K4/SM5K5
RECOMMENDED OPERATING CONDITIONS
(SM5K3/5K5)
PARAMETER Supply voltage Instruction cycle Main clock frequency (OSCIN-OSCOUT) SYMBOL VDD TSYS fOSC CONDITIONS VDD = 2.2 to 5.5 V VDD = 5.0 V 10% VDD = 2.2 to 5.5 V VDD = 5.0 V 10% RATING 2.2 to 5.5 2 to 61 1 to 61 1 M to 32.768 k 2 M to 32.768 k UNIT V s Hz
(SM5K4)
PARAMETER Supply voltage Instruction cycle Main clock frequency (OSCIN-OSCOUT) SYMBOL VDD TSYS fOSC CONDITIONS VDD = 2.7 to 5.5 V VDD = 5.0 V 10% VDD = 2.7 to 5.5 V VDD = 5.0 V 10% RATING 2.7 to 5.5 2 to 5 1 to 5 1 M to 400 k 2 M to 400 k UNIT V s Hz
Degree of fluctuation frequency : 20%
OSCILLATION CIRCUIT
* SM5K3/5K5
OSCIN Rf RD Rf C1 Oscillator C2
Rf = 33 k (fosc = 1.67 MHz, TYP.)
* SM5K4
OSCOUT OSCIN OSCOUT
Reference only : Circuit configuration varies according to oscillator used.
NOTES :
* The typical oscillation frequency shall be determined in consideration of operating condition and fluctuation frequency. * Mount Rf, RD, C1, C2, Oscillator (SM5K3/5K5)/Rf (SM5K4) as close as possible to the oscillator pins of the LSI, in order to reduce an influence from floating capacitance. * Since the value of resistor Rf, RD, C1, C2, Oscillator (SM5K3/5K5)/Rf (SM5K4) varies depending on circuit pattern and others, the final Rf, RD, C1, C2, Oscillator (SM5K3/5K5)/Rf (SM5K4) value shall be determined on the actual unit. * Don't connect any line to OSCIN and OSCOUT except oscillator circuit. * Don't put any signal line across the oscillator circuit line. * On the multilayer circuit, do not let the oscillator circuit wiring cross other circuit. * Minimize the wiring capacitance of GND and VDD .
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SM5K3/SM5K4/SM5K5
DC CHARACTERISTICS
* SM5K3
PARAMETER SYMBOL VIH1 VIL1 Input voltage VIH2 VIL2 IIL1 Input current IIH1 IIL2 IIH2 IOL1 IOH1 Output current IOL2 IOH2 IOH3 VIN = 0 V VIN = VDD VIN = 0 V VIN = VDD VO = 1.0 V VO = VDD - 0.5 V VO = 1.5 V VO = VDD - 0.5 V VOH = VDD - 1.0 V fOSC = 2 MHZ IDD fOSC = 1 MHz VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD = = = = = = = = = = = = = 2.2 4.5 2.2 4.5 2.2 4.5 2.2 4.5 2.2 4.5 4.5 2.2 4.5 to to to to to to to to to to to to to 3.3 5.5 3.3 5.5 3.3 5.5 3.3 5.5 3.3 5.5 5.5 3.3 5.5 V V V V V V V V V V V V V 5 15 0.3 1.0 1.2 5 0.3 1.0 0.15 0.5
(TOPR = -20 to +70C, TYP. value : VDD = 5.0 or 3.0 V, Unless otherwise noted.)
CONDITIONS MIN. 0.8 x VDD 0 0.9 x VDD 0 2 25 TYP. MAX. VDD 0.2 x VDD VDD 0.1 x VDD 90 250 2 10 10 UNIT NOTE V V A A 1 2 3 4
VDD = 2.2 to 3.3 V VDD = 4.5 to 5.5 V
25 70 1.0 1.0 15 25 1.5 2.2 5.0 9.0 2.0 2.4 1 200 300 600 20 760 200 400 20 15 220 10
mA
5
mA mA 2 500 800 1 200 120 1 500 600 900 75 2 40 450 2 4.0 5.0 6.0 LSB A A bit A
6 7
fOSC = 32.768 kHz VDD = (Crystal OSC mode) VDD = fOSC = 2 MHz VDD = fOSC = 1 MHz VDD = IHLT Supply cerrent fOSC = 32.768 kHz VDD = (Crystal OSC mode) VDD = Ceramic OSC mode ISTOP fOSC = 32.768 MHz VDD = (Crystal OSC mode) VDD = A/D in operation IVR VDD = A/D in stop Resolution Differential fOSC = 1 MHz VDD = linearity error TOPR = 25C A/D Sequential fOSC = 1 MHz VDD = conversion linearity error TOPR = 25C fOSC = 1 MHz Total error VDD = TOPR = 25C
2.2 to 3.3 V 4.5 to 5.5 V 2.2 to 3.3 V 4.5 to 5.5 V 2.2 to 3.3 V 2.2 to 3.3 V 2.2 to 3.3 V 4.5 to 5.5 V 4.5 to 5.5 V VR = 5.0 V VR = 5.0 V VR = 5.0 V
8
9 10
2.5 3.2 4.0
NOTES :
1. Applicable pins : P12, P13, P20-P23, P30-P33 (digital input mode), P40-P43 P50-P53 2. Applicable pins : OSCIN, RESET, P10, P11 3. Applicable pins : RESET, P10-P13, P20-P23, P40-P43, P50-P53 (digital input mode) 4. Applicable pins : P30-P33 (analog input mode) 5. Applicable pins : P00-P03 (high current mode) 6. Applicable pins : P20-P23, P40-P43, P50-P53 (output mode) 1 2 7. Applicable pins : P30-P33 8. No load (A/D conversion is stop.) 9. A/D conversion in operation (operation enable) 10. A/D conversion in stop (operation disable)
1 In case of 32-pin SOP and 36-pin QFP. 2
(In case of 30-pin SDIP, P52 dose not exist. In case of 28-pin SOP, P50-P53 do not exist.) P3 ports are normally used for input ports with pull-up resistor. These ports can be also used.
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SM5K3/SM5K4/SM5K5
* SM5K4
PARAMETER SYMBOL VIH1 VIL1 Input voltage VIH2 VIL2 IIL1 Input current IIH1 IIL2 IIH2 IOL1 IOH1 Output current IOL2 IOH2 IOH3 IDD IHLT VIN = 0 V VIN = VDD VIN = 0 V VIN = VDD VO = 1.0 V VO = VDD - 0.5 V VO = 1.5 V VO = VDD - 0.5 V VOH = VDD - 1.0 V fOSC = 2.0 MHz fOSC = 1.0 MHz VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD = 2.7 to 3.3 V = 4.5 to 5.5 V = 2.7 to 3.3 V = 4.5 to 5.5 V = 4.5 to 5.5 V = 2.7 to 3.3 V = 4.5 to 5.5 V = 4.5 to 5.5 V = 4.5 to 5.5 V = 2.7 to 3.3 V = 4.5 to 5.5 V = 4.5 to 5.5 V = 4.5 to 5.5 V 3 12 0.2 0.8 4.0 0.2 0.8 0.5
(TOPR = -20 to +85C, TYP. value : VDD = 5.0 or 3.0 V, Unless otherwise noted.)
CONDITIONS MIN.
0.8 x VDD 0 0.9 x VDD 0
TYP.
VDD = 2.7 to 3.3 V VDD = 4.5 to 5.5 V
1.0 15
25 70 1.0 1.0 15 25 1.5 2.2 9.0 2.0 2.4 1 200 300 600 760 400 130 220
MAX. VDD 0.2 x VDD VDD 0.1 x VDD 90 250 3.0 10 10
UNIT NOTE V V A A 1 2 3 4
mA
5
mA mA 2 800 900 1 400 1 700 1 000 5 350 500 3 10 4.0 5.0 6.0 2.0 MHz LSB
6 7
fOSC = 2.0 MHz Supply current fOSC = 1.0 MHz ISTOP VDD = 2.7 to 5.5 V A/D conversion IVR in operation A/D conversion in stop Resolution Differential fOSC = 1.0 MHz linearity error TOPR = 25C A/D Sequential fOSC = 1 MHz conversion linearity error TOPR = 25C fOSC = 1 MHz Total error TOPR = 25C Reference clock oscillator frequency fOSC
A
8
VDD = 2.7 to 3.3 V VDD = 4.5 to 5.5 V VDD = 2.7 to 5.5 V VDD = VR = 5.0 V VDD = VR = 5.0 V VDD = VR = 5.0 V 1.34
A A bit
9 10
2.5 3.2 4.0 1.67
VDD = 4.5 to 5.5 V, Rf = 33 k
NOTES :
1. Applicable pins : P12, P13, P20-P23, P30-P33 (digital input mode), P40-P43, P50-P53 1 2. Applicable pins : OSCIN, RESET, P10, P11 3. Applicable pins : RESET, P10-P13, P20-P23, P40-P43, P50-P53 (digital input mode) 1 4. Applicable pins : P30-P33 (analog input mode) 5. Applicable pins : P00-P03 (high current output) 6. Applicable pins : P20-P23, P40-P43, P50-P53 (output mode) 1 2 7. Applicable pins : P30-P33 8. No load (A/D conversion in stop) 9. A/D conversion in operation (A/D conversion enable) 10. A/D conversion in stop (A/D conversion disable)
1 In case of 32-pin SOP and 36-pin QFP.
(In case of 30-pin SDIP, P52 pin dose not exist. In case of 24-pin SSOP, P12, P13, P33, P50-P53 pins do not exist.) 2 P3 ports are normally used for input port with pull-up resistor. These ports can be also used as a suspected case of output port.
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SM5K3/SM5K4/SM5K5
* SM5K5
PARAMETER SYMBOL VIH1 VIL1 Input voltage VIH2 VIL2 IIL1 Input current IIH1 IIL2 IIH2 IOL1 IOH1 Output current IOL2 IOH2 VO = 0.5 V VO = VDD-0.5 V fOSC = 2 MHz IDD fOSC = 1 MHz VIN = 0 V VIN = VDD VIN = 0 V VIN = VDD VO = 1.0 V VO = VDD-0.5 V VDD = 2.2 to 3.3 V VDD = 4.5 to 5.5 V VDD = 2.2 to 3.3 V VDD = 4.5 to 5.5 V VDD = 2.2 to 3.3 V VDD = 4.5 to 5.5 V VDD = 2.2 to 3.3 V VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V VDD = 2.2 to 3.3 V 5 15 0.3 1.0 7 20 300 1 000 1 1 15 25 1.5 2.2 35 60 2 000 2 400 1 200 300 600 20 40 760 400 15 20 2 10 130 220 10 fOSC = 1 MHz VDD = VR = 5.0 V VDD = VR = 5.0 V VDD = VR = 5.0 V 2.5 3.2 4.0 4.0 5.0 6.0 LSB 2 500 800 1 200 120 160 1 500 900 60 90 2 10 25 300 450 2 A A bit 8 9 A 7 A 7 A 6 mA
(TOPR = -20 to +70C, TYP. value : VDD = 5.0 or 3.0 V, Unless otherwise noted.)
CONDITIONS MIN. 0.8 x VDD 0 0.9 x VDD 0 VDD = 2.2 to 3.3 V VDD = 4.5 to 5.5 V 2 25 25 70 TYP. MAX. VDD 0.2 x VDD VDD 0.1 x VDD 90 250 2 10 10 UNIT NOTE V V 1 2
A
3
A
4
5
VDD = 4.5 to 5.5 V fOSC = 32.768 kHz VDD = 2.2 to 3.3 V (Crystal OSC mode) fOSC = 2 MHz fOSC = 1 MHz VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V
Supply current
IHLT
fOSC = 32.768 kHz VDD = 2.2 to 3.3 V (Crystal OSC mode) VDD = 4.5 to 5.5 V Ceramic OSC mode VDD = 2.2 to 3.3 V fOSC = 32.768 kHz VDD = 2.2 to 3.3 V (Crystal OSC mode) VDD = 4.5 to 5.5 V A/D in operation A/D in stop VDD = 2.2 to 3.3 V VDD = 4.5 to 5.5 V VDD = 2.2 to 5.5 V
ISTOP
IVR
Resolution Differential A/D conversion
linearity error TOPR = 25C Sequential fOSC = 1 MHz linearity error TOPR = 25C Total error fOSC = 1 MHz TOPR = 25C
-8-
SM5K3/SM5K4/SM5K5
NOTES :
1. Applicable pins : P12, P13, P20-P23, P30-P33 (digital input mode), P40-P43, P50-P53 1 2. Applicable pins : OSCIN, RESET, P10, P11 3. Applicable pins : RESET, P10-P13, P20-P23, P40-P43, P50-P53 (digital input mode) 1 4. Applicable pins : P30-P33 (analog input mode) 5. Applicable pins : P00-P03 (high current port) 6. Applicable pins : P20-P23, P40-P43, P50-P53 (output mode) 1 7. No load (A/D conversion in stop) 8. A/D conversion in operation (operation enable) 9. A/D conversion in stop (operation disable) 1 In case of 32-pin SOP and 36-pin QFP. ( In case of 30-pin SDIP, P52 dose not exist. In case of 28-pin SOP, P50-P53 do not exist.)
Arithmetic and Logic Unit (ALU) and Carry Signal Cy
The ALU performs 4-bit parallel operation
4-bit data 4-bit data
ALU
Result of operation
SYSTEM CONFIGURATION A Register and X Register
The A register (or accumulator : ACC) is a 4-bit general purpose register. The register is mainly used in conjunction with the ALU, C flag and RAM to transfer numerical value and data to perform various operations. The A register is also used to transfer data between input and output pins. The X register (or auxiliary accumulator) is a 4-bit register and can be used as a temporary register. It loads contents of the A register or its content is transferred to the A register. When the table reference instruction PAT is used, the X and A registers load ROM data. A pair of A and X registers can accommodate 8-bit data.
3 A register EXAX instruction 3 X register 0 0
Areg
c
Fig. 2 ALU
The ALU operates binary addition in conjunction with RAM, C flag and A register. The carry signal Cy is generated if a carry occurs during ALU operation. Some instructions use Cy : ADC instruction sets/clears the content of the C flag; ADX instruction causes the program to skip the next instruction. Note that Cy is the symbol for carry signal and not for C flag.
Fig. 1 Data Transfer Example between A Register and X Register
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SM5K3/SM5K4/SM5K5
B Register and SB Register
* B register (BM, BL) The B register is an 8-bit register that is used to specify the RAM address. The upper 4-bit section is called BM register and lower 4-bit BL. * SB register The SB register is an 8-bit register used as the save register for the B register. The contents of B register and SB register can be exchanged through EX instruction.
3 BL register 0
3
0 BM register
B register
EX instruction (swap)
7 0
SB register
Fig. 3 B Register and SB Register
Data Memory (RAM)
The data memory (RAM) is used to store data up to 4 x 16 x 8 = 512 bits.
Word (0-FH)
BL BM 0 1 2
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
File
(0-7)
3 4 5 6 7 1 word = 4-bit
Fig. 4 RAM File and Word
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SM5K3/SM5K4/SM5K5
Program Counter PC and Stack Register SR
The program counter PC specifies the ROM address. The PC consists of 12-bit as shown in Fig. 5 : The upper 6-bit (PU) represents a page while the lower 6-bit (PL) denotes a step. The PU section is a register and the PL section, a binary counter.
Program counter PC Page Step
Execution of interrupt handling and the table reference instruction PAT also automatically uses 1 stage of the stack register SR.
PU
MSB
PL
LSB
Push SR ( level 1 ) SR ( level 2 ) SR ( level 3 ) SR ( level 4 )
Stack register SR
Pop
Fig. 5 Program Counter PC and Stack Register SR
Program Memory (ROM)
The ROM is used to store the program. The capacity of the ROM is 2 048-step (32-page by 64step. See Fig. 6). The configuration of the ROM and program jumps are illustrated in Fig. 7.
Specifies a page (Pages 00H-1FH) PU
Specifies a page (Pages 00H-3FH) PL
Fig. 6 Page and Step for ROM
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SM5K3/SM5K4/SM5K5
PU (page) 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH
Number in a circle is a step number in the program jump. 1 Start address upon hardware reset
PU (page) 10H
TLxy
Front cover of subroutine TRS Interrupt
RTN
11H 12H
2
RTN TRSx
1 3
Standby released
1
2
13H 14H 15H 16H
Reference to the table during execution of PAT instructions
TRSx
TLxy
1
17H 18H 19H
TRx
1
TRx
1
1AH 1BH
RTN
2
1CH 1DH 1EH 1FH
Last page, last step (1F3FH)
CALLxy
Fig. 7 ROM Configuration and Program Jump Example
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SM5K3/SM5K4/SM5K5
Output Latch Register and Mode Register
The SM5K3/5K4/5K5 contain 6 output-latch registers and 8 mode-registers which either latch contents of output ports or control some functions of the SM5K3/5K4/5K5. These registers, their functions and available transfer instructions are shown in Table 1 below. An output latch register sets the output level of the pin to which it is connected. Refer to the section of "MODE REGISTERS" concerning about the details mode registers.
Table 1 Output Latch Registers and Mode Registers SYMBOL P0 P1 P2 P3 R3 P4 P5 R8 R9 RA RB RC RE RF 8-bit register FUNCTION Output register Input register I/O register (independent) Input register (and analog input) Control register I/O register I/O register A/D data/control register A/D data register Timer/counter register Timer/modulo register Timer control register Interrupt mask register P2 directional register OUT O - - - - - - - - - - - - - INL - O - - - - - - - - - - - - OUT O - O - O O O O O O O O O O IN/TPB - O O O - O O O O O O O O O ANP/ORP O - O - - O O - - - - - - - CONTENT OF BL 0 1 2 3 3 4 5 8 9 A B C E F
NOTE :
Bit 4 (R84) in the R8 register is read only. (Read or write operation of this bit does not affect any other operation.)
- 13 -
SM5K3/SM5K4/SM5K5
FUNCTIONAL DESCRIPTION Hardware Reset Function
Reset function initializes the SM5K3/5K4/5K5 systems. When the input on the RESET pin goes Low, the system enters reset condition after 2 command cycles. After the RESET pin goes High level, the reset condition is removed as the input pulse from OSCIN pin repeats 215 times, forcing the program counter to start at 0 page and 0 address. Initialized status of the system immediately after resetting is shown below.
Table 2 Status of Flags and Registers Immediately after Reset FLAG REGISTER PC SP RAM Register A Register X P0, P2, P4, P5 output latch register Timers (RA, RB), divider STATUS 0 Level 1 Undefined Undefined Undefined 0 0 FLAG REGISTER IFA flag IFB flag IFT flag IME flag C flag BM, BL registers, SB register R3, R8, R9, RC, RE, RF STATUS 0 0 0 0 Undefined Undefined 0
The content of the bit R84 is undefined because it is read only.
Reset causes the following changes. 1) I/O pins are set input. 2) All mode registers are reset. 3) Output latch register P0 is reset, causing P00 to P03 pins go High level. 4) Interrupt request flags (IFA, IFB, and IFT), interrupt master enable flag (IME) are reset, disabling all interrupts.
Standby Feature
The standby function saves power by stopping the program whenever it is not necessary to run. The mode in which the microcomputer is executing the program is called the run mode and the mode in which it stops the program is called the standby mode. Standby mode is further divided into two modes : stop mode and halt mode, one of which is selected by halt instruction or stop instruction. Upon removal of standby condition, the SM5K3/5K4/5K5 return from the standby mode to the normal run mode. To enter the standby mode, select either stop mode or halt mode whichever is appropriate (Fig. 8).
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SM5K3/SM5K4/SM5K5
Operation mode
Run HALT command
Standby mode
HALT mode HALT mode release event
Normal operation
Run STOP command STOP mode
STOP mode release event
Fig. 8 Operation Shift of Program
* Blocks stopped during standby mode In the halt mode The system clock generating circuit stops during the halt mode, deactivating all the blocks driven by the system clock. The main clock and dividers remain active. This means that timers can be used while in the halt mode. Both internal and external clocks can be used as the count clock.
In the stop mode The main clock and system clock stop upon entering the stop mode. Therefore, only timers using the external clock remain active. * Counters that the system retains during standby mode The contents that will be retained in the halt mode will also be retained in the stop mode. These items are shown in Table 3.
Table 3 System Contents Secured During Standby Mode FLAG IFA flag IFB flag IFT flag IME flag C flag REGISTER A register X register BM, BL register SP SR OUTPUT LATCH REGISTER/MODE REGISTER P0, P2, R3, P5 R8, R9, RA, RB RC, RE, RF OTHER RAM
* Releasing events of standby mode (6-type)
RELEASING EVENT Reset input Low level input on P10 pin Low level input on P11 pin Low level input on P12 pin Low level input on P13 pin Timer overflow FLAG - IFA IFB - - IFT INT/EXT External External External External External Internal MASKABLE / NONMASKABLE Nonmaskable Maskable Maskable Nonmaskable Nonmaskable Maskable PRIORITY - 1 2 - - 3
- 15 -
SM5K3/SM5K4/SM5K5
* Usage of halt mode and stop mode The system returns back to the normal operation mode upon occurring of a standby mode releasing condition. The halt mode should be used when the system must enter and exit normal operation frequently as in the case of key operation. The halt mode should also be used to keep timers that are operating from the internal clock, while in the standby mode. The stop mode further saves power than the halt mode but requires slightly longer time to return to
the normal mode. Therefore, the stop mode should be used when the system will not be required to return to the normal mode in a short time.
Interrupt Feature
The interrupt block consists of mask flags (bits RE0, RE1 and RE2), IME flag and interrupt request handling circuit. Fig. 9 shows the configuration of the interrupt block.
Mask flag (mode register RE)
RE2 RE1 RE0 Stack register SR Program counter PC
Interrupt request flag
I FA
INT signal
I FB IME I FT
Interrupt handling circuit Interrupt enable flag (master enable flag)
Fig. 9 Interrupt Block Diagram
* Interrupt used with SM5K3/5K4/5K5 Interrupt event occurs on the falling edge of P10 or P11 pin input, or the overflow at the timer. These events set flags IFA, IFB and IFT respectively, that then serve as interrupt request flag.
Table 4 shows interrupt handling priority level and jump address.
Table 4 Interrupt Event Summary INTERRUPT EVENT (REQUEST FLAG) Falling edge of input on P10 (IFA) Falling edge of input on P11 (IFB) Timer overflow (IFT) JUMP ADDRESS PAGE STEP 2 0 2 2 2 4 PRIORITY ORDER 1 2 3 INTERRUPT MASK FLAG RE0 RE1 RE2
- 16 -
SM5K3/SM5K4/SM5K5
* IME flag (master enable flag) The IME enables or disables all interrupts at the same time. The IE command, when executed, sets the IME flag and enables the interrupt specified by the mask flag setting. The ID command resets the IME flag, disabling process of any interrupt request. Setting the IME flag to reset after releasing hardware reset, all interrupts are inhibited. * Mode register RE (interrupt mask flag) The mode register RE (RE0, RE1 and RE2; interrupt mask flag) individually enables or disables three type of interrupts.
Timer/Counter
The SM5K3/5K4/5K5 have a pair of built-in timer/counter. The timer/counter are used to handle periodic interrupts and to count. The overflowing timer can be used to disable the halt mode. The timer/counter serve as interval timer. The timer/counter consists of an 8-bit count register RA, modulo register RB (for counter initial value setting), 15-bit divider and 4-bit mode register RC (for count clock selection). The configuration of the timer/counter is shown in Fig. 10.
A 0 30
X 3
After setting BL = 0BH OUT command ( RB[ X, A ] ) IN command ( [ X, A ]RB )
Count clock selsctor
Modulo register ( RB register ) 0 34 Count register ( RA register ) 0 A 0 30 34 X 3 7
After setting BL = 0AH IN command
fSYS / 27 fSYS / 2 15
7
After setting BL = 0AH OUT command
fSYS
Divider
I FT
Interrupt request flag
System clock
P11 pin ( external event clock ) Mode register ( RC register )
Fig. 10 Configuration of Timer/Counter
* Selecting count clock A count clock is selected by the bit settings in the mode register RC.
Table 5 Count Clock Selection LOWER 2-BIT OF RC BITS 1 0 0 1 1 0 0 1 0 1 SELECTED COUNT CLOCK fSYS (system clock) fSYS/27 fSYS/215 External event clock (P11)
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SM5K3/SM5K4/SM5K5
A/D Conversion
The SM5K3/5K4/5K5 are provided with a built-in 10-bit A/D converter having 4-channel multiplexer analog inputs. The A/D converter operates in A/D conversion mode and comparison mode. In the A/D conversion mode, the converter converts the analog input from the P3 pin to the digital value; and in the comparison mode, it compares the input analog amplitude with that of a reference voltage set inside the SM5K3/5K4/5K5. The P30 to P33 pins can be used as analog voltage inputs. One or more of these 4 inputs can be set to assume A/D pin by the bit operation of the mode register R3. One of these A/D pins is further set as analog input
Normal input pin
by the bit operation of the mode register R8. The A/D converter is controlled by the bits set in the mode register R8. For details of the mode register R8, refer to " MODE REGISTERS R8 ". Configuration of the A/D converter is illustrated in Fig. 11. CAUTIONS
* Keep the A/D converter reference voltage on the VR pin equal to or below VDD. * Do not apply the voltage to the VR pin before VDD is applied. * Connect AGND to GND.
P30 P31 P32 P33 A/D pins
VR Multiplexer 10-bit D/A Comparator Control circuit AGND
Changeover
R3 register
A/D control, data (mode register R8 )
A/D data ( Mode register R9 )
A register
X, A registers
X, A registers
Fig. 11 A/D Converter Block Diagram
A/D CONVERSION MODE In the A/D conversion mode, the converter converts the analog input voltage to the digital value. The analog input voltage is successively compared with the internal voltage charged on the weighted capacitor array until its digital equivalent is determined. The resultant digital data is stored into the mode registers R8 and R9. The conversion requires 152.5 s (main clock at 400 kHz/system clock at 5 s) or 1.86 ms (main clock at 32.768 kHz/system clock at 61 s).
COMPARISON MODE In the comparison mode, the analog voltage from one of P30 to P33 pins is compared, in amplitude, with internally generated voltage whose value is set by the mode registers R8 and R9. The result data of the comparison is saved into the bit 4 (bit R84) position of the mode register R8. The comparison cycle lasts 62.5 s (main clock at 400 kHz, system clock at 5 s) or 763 s (main clock at 32.768 kHz/system clock at 61 s).
- 18 -
SM5K3/SM5K4/SM5K5
MODE REGISTERS
The registers which control functions of the SM5K3/5K4/5K5 and which serve as counter/timer are commonly referred to as "mode registers". In the SM5K3/5K4/5K5, R8 to RB are 8-bit mode registers; and R3, RC, RE and RF are 4-bit mode registers. To set data into the mode registers, the OUT command is used; and to check the contents of the mode registers IN command is used. Bit 5 A/D operation enable/disable flag 0 | Disable (A/D power source off) 1 | Enable (A/D power source on) Bit 4 Storages of comparison result (read only) 0 | P3i pin voltage < internal setting voltage 1 | P3i pin voltage > internal setting voltage (i = 3 to 0) Bit 3 S/R flag (start/clear) 0 | End of operation (or stop) 1 | Start of operation (or in operation) Bit 2 Operation mode selection 0 | A/D conversion 1 | Comparison Bits 1 to 0 Select one of A/D pins as A/D conversion 00 | P30 01 | P31 10 | P32 11 | P33
When operation is end, these bits are cleared.
R3 (A/D pin selection register)
Any pin on 4-pin port P3 can be set accommodate analog voltage (hereafter called A/D pin). Bit 3 0
Bit i (i = 3 to 0) Sets P3i pin to either general purpose input or A/D pin 0 | (General purpose) input 1 | A/D input
Select one pin which is to be selected by mode register R8.
R8 (A/D conversion control & A/D data register)
An 8-bit register used to control A/D conversion and storing part of A/D conversion result. It also stores the results of comparison. Bit 7 0
R9 (A/D data register)
The register to store the upper 8-bit of 10-bit data resulting from A/D conversion. Bit 7 0
Bits 7 to 6 Storage of A/D conversion result (A/D conversion mode) and setting of internal voltage (comparison mode) * Use as part of a 10-bit data ragister in combination with mode register R9. * Bit R86 is the LSB. * Store lower 2-bit of converted data in A/D conversion mode. * Use as lower 2-bit of internal voltage setting data in comparison mode.
Bit i (i = 7 to 0) Storages of A/D conversion result (A/D conversion mode) and setting of internal voltage (comparison mode) * Uses as part of a 10-bit data register in combination with mode register R8. * Bit R97 is the MSB. * Stores upper 8-bit of A/D conversion result. * Uses as upper 8-bit of internal voltage setting data in comparison mode.
- 19 -
SM5K3/SM5K4/SM5K5
RA (Count register)
Bit 7 0
Bit i (i = 7 to 0) Count clock input register * Uses as counter part of timer/counter (count clock input). * Loads the content of RB to RA when the RA overflows or when OUT command (BL = 0AH) is executed. RARB * Loads the content of RA to X and A registers upon execution of IN command (BL = 0AH). (X, A)RA * Bit 7 = MSB, bit 0 = LSB
Bit 2 (Unused) Bits 1 to 0 Select the source clock to the timer. 00 | fSYS (system clock) 01 | fSYS/27 10 | fSYS/215 11 | Falling edge input on P11 pin
RE (Interrupt mask flag)
Bit 3 0
RB (Modulo register)
Bit 7 0
Bit i (i = 7 to 0) Count initial value storage register * Uses as modulo register of timer/counter * Loads the content of RB to X and A registers upon execution of IN command (BL = 0BH) : X = upper bits, A = lower bits. (X, A)RB * Loads the contents of X and A registers to RB upon execution of OUT command (BL = 0BH) : X = upper bits, A = lower bits. RB(X, A) * Bit 7 : MSB, Bit 0 : LSB
Bit 3 (Unused) Bit 2 Removes overflow interrupt from timer or standby condition. 0 | Disable 1 | Enable Bit 1 Interrupts on the falling edge of input from P11 pin, or releases of standby mode by the Low input from P11 pin. 0 | Disable 1 | Enable Bit 0 Interrupts on the falling edge of input on P10 pin, or releases of standby mode by the Low input from P10 pin. 0 | Disable 1 | Enable
RF (P2 port direction register)
Bit 3 0
RC (Timer control)
Bit 3 0
Bit i (i = 3 to 0) Selection of input pin/output pin 0 | Set P2i pin to input. 1 | Set P2i pin to output.
Bit 3 Starts up count of the timer. 0 | Stop 1 | Start
- 20 -
SM5K3/SM5K4/SM5K5
I/O Ports
The SM5K3/5K4/5K5 have 24 ports : 8-input, 4output and 12-I/O port. To verify the input, use suitable instruction to transfer the input on the pin directly to the A register. To select the output latch register to which the content of the A register is to be transferred, and to select the input port from which the signal or data is to be transferred to the A register, use the BL register. For details of BL settings and associated ports, refer to Table 1. * Port P00 to P03 (CMOS inverting output port) The data transfers in 4-bit string (use OUT or OUTL instruction) or in unit of 1-bit (use ANP or ORP instruction). * Port P10 to P13 (input port with pull-up resistor) The data transfers in unit of 4-bit. This port can be used as standby/external interrupt input or count pulse input. The P1 port can also be used as a standby release port without requiring specific setting on P12 and P13 pins. Pins P10 and P11 require settings through the mode resister RE. When using the P1 port as an external interrupt input, use pins P10 and P11 with suitable settings in the mode register RE. When using the P1 port as the count pulse input, use P11 pin. * Port P20 to P23 (I/O port with pull-up resistor) Each bit can be independently be set its direction and can be transferred independently or in combination of other 3-bit. The direction of the bits is determined by the RF register. After reset, the P2 port is set input. * Port P30 to P33 (input port with pull-up resistor) The data transfers in unit of 4-bit. The port can also be used as A/D analog voltage input. To use the P3 port as the A/D port, set the mode register R3. * Port P40 to P43 (I/O port with pull-up resistor) The data transfers in unit of 4-bit. When set output, content of each bit can be set. Executing the input instruction (IN) sets the P4 ports (P40 to P43) to input; and executing output instruction (OUT, ANP or ORP) sets the port to output. After reset, the P4 port is set input. * Port P50 to P53 (I/O port with pull-up resistor) The data transfers in unit of 4-bit. When set output, content of each bit can be set. Executing the input instruction (IN) sets the P5 ports (P50 to P53) to input; and executing output instruction (OUT, ANP or ORP) sets the port to output. After reset, the P5 port is set input.
Flags
The SM5K3/5K4/5K5 have 4 flags (C flag and interrupt request flags [IFA, IFB, IFT] ), which are used to perform setting and judgments.
- 21 -
SM5K3/SM5K4/SM5K5
System Clock Generator and Dividers
* System clock generator The system clock is the divided-by-two main clock applied through OSCIN and OSCOUT (See Fig. 12). The system clock generator is shown in Fig. 13. One system clock cycle period is equal to one instruction execution time when the instruction consists of 1 word. When the ceramic oscillator runs at 400 kHz, the system clock fsys is 200 kHz. This means that the instruction execution time is 5 s/word. Using a 32.768 kHz crystal oscillator generates 16.384 kHz fsys and the instruction execution time is 61 s/word. The system clock can be used as count input pulse to the timer.
Main clock (fOSC) System clock (fSYS)
Fig. 12 Main Clock and System Clock
* Divider The divider consists of 15 divided-by-two dividers, providing 2 (fSYS/27, fSYS/215) of 4 count clocks that are fed to the counter RA from the system clock.
OSCIN
Its configuration is shown below. The divider can be cleared by using the DR instruction.
System clock generator (divided-by-two main clock)
OSCOUT
fSYS/2
7
CG
1 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
fSYS/2
15
fSYS ( System clock )
2
Divider (can be cleared by DR instruction)
Fig. 13 System Clock Generator and Divider
* Oscillator mask option Selection of type of oscillator, ceramic or crystal, is made by mask option.
- 22 -
SM5K3/SM5K4/SM5K5
INSTRUCTION SET Definition of Symbols
: Content of RAM at the address defined by the B register. : Transfer direction : Logical OR : Logical AND : Exclusive OR Ai : An i bit of A register (i = 3 to 0) Push : Saves the contents of PC to stack register SR. Pop : Returns the contents saved in the stack register back to PC. Pj : Indicates output latch register or input register. Pj ( j = 0, 1, 2, 3, 4, 5) Rj : Mode register. Rj register ( j = 3, A, B, C, E, F) ROM ( ) : Content stored in ROM location defined by the value in ( ). CY : Carry in ALU (independent of C flag) The CY(carry) is a signal which is generated when the ALU has been carried by the execution of a command. It is different from the C flag. X : Used to represent a group of bits in the content of a register or memory. For example, the X in the LDAX instruction denotes the lower 2 digits (I1 and I0) of A register. M
Instruction Summary
MNEMONIC MACHINE CODE OPERATION
TR x TL xy TRS x CALL xy RTN RTNS RTNI LAX x LBMX x LBLX x LDA x EXC x
ROM Addressing Instructions PLx (I5-I0) 80 to BF E0 to E7, 00 to FF C0 to DF F0 to F7 00 to FF 7D 7E 7F PUx (I11-I6) PLy (I5-I0) Push, PU01H, PLx (I4, I3, I2, I1, I0) Push, PUx (I11-I6) PLy (I5-I0) Pop
Pop, Skip the next step

Pop, IME1
Data Load Instructions Ax (I3-I0) 10 to 1F BMx (I3-I0) 30 to 3F BLx (I3-I0) 20 to 2F 50 to 53 54 to 57 AM, BMiBMi x (I1, I0), (i = 1, 0) MA, BMiBMi x (I1, I0), (i = 1, 0) MA, BLBL+1 BMiBMi x (I1, I0), (i = 1, 0) Skip the next step, if result of BL = 0 MA, BLBL-1
EXCI x
58 to 5B
EXCD x
5C to 5F
BMiBMi x (I1, I0), (i = 1, 0) Skip the next step, if result of BL is = FH AX-reg X-regA BMA BLA BSB
* A bit in a register is affixed to the register symbol, e.g. a bit (i = 0, 1, 2, 3....) of X register is expressed as Xi and P (R) register as P (R) i. * Increment means binary addition of 1H and decrement addition of FH. * Skipping an instruction means to ignore that instruction and to do nothing until starting the next instruction. In this sense, an instruction to be skipped is treated as an NOP instruction. Skipping 1-byte instruction requires 1-cycle, and 2-byte instruction 2-cycle. Skipping 1-byte 2-cycle instruction requires 1-cycle.
EXAX ATX EXBM EXBL EX
64 65 66 67 68
- 23 -
SM5K3/SM5K4/SM5K5
MNEMONIC
MACHINE CODE
OPERATION
MNEMONIC
MACHINE CODE
OPERATION
ADX x ADD ADC COMA INCB DECB
Arithmetic Instructions AA+x (I3-I0) 00 to 0F Skip the next step, if CY = 1 AA+M 7A 7B 79 78 7C AA+M+C, CCY Skip the next step, if CY = 1 - AA BLBL+1, Skip the next step, if result of BL = 0 BLBL-1, Skip the next
INL OUTL ANP ORP IN
I/O Instructions AP1 70 P0A 71 72 73 74 PjPj
PjPj A ( j = 0, 2, 4, 5) APj ( j = 1, 2, 3, 4, 5) X-reg, ARj ( j = 8, 9, A, B) ARj ( j = C, E, F) PjA ( j = 0, 2, 4, 5)
A ( j = 0, 2, 4, 5)
step, if result of BL = FH Test Instructions 6F 6E 48 to 4B 6B 4C to 4F 6C 6D 69 Skip the next step, if A = M Skip the next step, if C = 1 Skip the next step, if Mi = 1, (i = 3 to 0) Skip the next step, if A = BL Skip the next step, if P (R) i = 1, (i = I1, I0) Skip the next step, if IFA = 1 IFA0 Skip the next step, if IFB = 1 IFB0 Skip the next step, if IFT = 1
OUT
75
RjX-reg, A ( j = 8, 9, B) RARB RjA ( j = 3, C, E, F) Push PU04H, PL(X1, X0, A) X-regROMH, AROML Pop
TAM TC TM x TABL TPB x TA TB TT
Table Search Instruction
PAT
6A
DR
Divider Operation Instruction 69 Divider (f0-f15) clear 03 Special Instructions 76 77 00 Standby mode (STOP) Standby mode (HALT) No operation
STOP HALT NOP
SM x RM x SC RC IE ID
IFT0 02 Bit Operation Instructions Mi1 (i = 3 to 0) 44 to 47 40 to 43 61 60 63 62 Mi0 (i = 3 to 0) C1 C0 IME1 (Interrupt enable) IME0 (Interrupt disable)
- 24 -
SM5K3/SM5K4/SM5K5
SYSTEM CONFIGURATION EXAMPLE
* Charger controller
VDD
+ DC supply source P00 P01 P02 P03 VDD P20 VR P21 P40 P41 P42
Switching circuit
Battery
To 10-bit A/D converter
SM5K3/5K5
OSCIN OSCOUT P30 RESET GND AGND
VDD
+ DC supply source P00 P01 P02 P03 VDD P20 VR P21 P40 P41 P42 SM5K4 OSCIN
Switching circuit
Battery
To 10-bit A/D converter
P30
OSCOUT RESET GND AGND
- 25 -
SM5K3/SM5K4/SM5K5
30 SDIP (SDIP030-P-0400)
30
16 8.6 0.2
0.2
1
4.4 0.2
27.2 0.25
15
0.51MIN.
3.85
10.16 TYP.
0.25
M
0.2
1.778 TYP.
0.46 0.1
0 -1
0.25
0.1
5
32 SOP (SOP032-P-0525)
0.4 32
0.1
3.25
1.27 TYP. 17
0.15 (1.4)
M
11.3 0.2
1 20.6 0.2
16 0.15
(1.4)
14.1 0.4
(12.5) 2.7 0.2 0.15
0.05
1.275 0.1 0.1
0.1
- 26 -
SM5K3/SM5K4/SM5K5
36 QFP (QFP036-P-1010)
0.8TYP. 27 M 0.38 0.1 19 0.15 0.05 (1.75) 18 10.0 0.2 13.5 0.4 (11.5) 0.85 0.2 1.45 0.2 0.1 0.1 Package base plane 0.15 0.05 1.025 2.2 0.2 (10.6) 0.15 10 (1.75) (1.75) 1 10.0 0.2 13.5 0.4 9 (1.75) 0.12 0.4 0.1 28 1.27 TYP. 15 (1.7) 0.15 0.1 (1.7) 0.1 0.1 12.0 0.3 8.6 0.2 1 18.0 0.2 14 M
0.15
28
36
28 SOP (SOP028-P-0450)
- 27 -
SM5K3/SM5K4/SM5K5
24 SSOP (SSOP024-P-0275)
0.27 0.1 24
0.65 TYP. 13
0.15
M
6.0 0.2
7.6 0.4
7.8
0.2
1.05 0.1
1
12 0.15 0.45
0.15 0.05
0.15
- 28 -
0.1 0.1
(6.6)

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